1. Field of the Invention
The present invention relates to a semiconductor memory device capable of memorizing multiple-value data and a control method for the semiconductor memory device.
2. Description of the Related Art
A NAND flash memory wherein EEPROM (Electrically Erasable and Programmable Read Only Memory) is used has been proposed as a non-volatile semiconductor capable of electrically rewriting data. In the NAND flash memory, sources and drains of a plurality of memory cells adjacently placed are serially connected, and the multiple memory cells serially connected is connected to a bit line as a unit. In the NAND flash memory, the data is written in and read from all or half of the plural cells placed in a row direction.
Recently, a multiple-value memory for memorizing a plural data in a cell of the NAND flash memory has been developed. No. 2001-93288 of the Publication of the Unexamined Japanese Patent Applications discloses a data writing method, and the like, for the multiple-value NAND flash memory, which is an example the technology.
FIG. 22 shows the data writing method recited in the document mentioned above. When the data is written in the memory cell, a threshold voltage of the memory cell is not changed by the writing operation in the case that the write data constituting a data in a first or second page is “1”. In other words, there is no change in the data in the memory cell, that is, the data is not written in the cell. The threshold voltage of the memory cell is changed by the writing operation in the case that the write data constituting the data in the first or second page is “0”. In other words, the data in the memory cell is changed, that is, the data is written in the cell.
Assuming that the data in the memory cell in an erased state is “0” (data “11”: data “1” in the second page, data “1” in the first page), first, the data in the first page is written in the memory cell. When the write data is “1”, the data in the memory cell remains “0” (data “11). When the write data is “0”, the data in the memory cell shifts to “1” (data “10”).
Next, the data in the second page is written in the memory cell. In the case that the write data “0” is supplied from outside to the memory cell whose data shifts to “1” (data “10”) by the write operation in the first page, the data in the memory cell shifts to “2” (data “00”). In the case that the write data “0” is supplied from outside to the memory cell whose data remains “0” (data “11”) by the write operation in the first page, the data in the memory cell shifts to “3” (data “01”).
FIG. 23 shows the data reading method recited in the foregoing document. When the data in the second page is read from the memory cell, the read data is “1” in the case that the data in the memory cell is “0” (data “11”) or “1” (data “10”), while the read data is “0” in the case that the data in the memory cell is “2” (data “00”) or “3” (data “01”). Therefore, the data can be read from the memory cell if it is judged if the data in the memory cell is at most “1”, or at least “2”. Accordingly, the data is read from the memory cell by setting a word-line voltage when the data is read to a second judgment level which is a voltage between “1” and “2”.
The read data is “1” if the data in the memory cell is “0” (data “11) or “3” (data “01) in reading the data in the first page, while the read data is “0” if the data in the memory cell is “1” (data “10”) or “2” (data “00”). Therefore, the data in the first page can be read by judging if the data in the memory cell is at least “0” or at least “1”, and if the data in the memory cell is at most “2” state or “3”. More specifically, the data in the first page can be read in the two reading operations, which are respectively the reading operation where the word-line voltage when the data is read is set to a first judgment level which is a voltage between “0” and “1”, and the reading operation where the word-line voltage is set to a third judgment level which is a voltage between “2” and “3”.
FIG. 21 shows a schematic constitution of the conventional non-volatile semiconductor memory device, for example, a structure of the NAND flash memory for memorizing quaternary data (two bits). A memory cell array 1 includes a plurality of bit lines, a plurality of word lines and a common source line, wherein memory cells comprising, for example, EEPROM cells, and capable of electrically rewriting data are arranged in a matrix shape. A bit line control circuit 2 for controlling the bit lines and a word line control circuit 6 are connected to the memory cell 1.
The bit line control circuit 2 includes a plurality of data memory circuits as described later. The bit line control circuit executes a processing in which the data in the memory cell in the memory cell array 1 is read via the bit line, a processing in which a state of the memory cell in the memory cell array 1 is read via the bit line, and a processing in which a write control voltage is applied to the memory cell in the memory cell array 1 via the bit line so that the data is written in the memory cell. A column decoder 3 and a data input/output circuit 4 are connected to the bit line control circuit 2. Any of the data memory circuits in the bit line control circuit 2 is selected by the column decoder 3. The data in the memory cell read via the selected data memory circuit is outputted outside from the data input/output terminal 5 via the data input/output circuit 4. The write data inputted to the data input/output terminal 5 from outside is inputted to the data memory circuit via the data input/output circuit 4. The data memory circuit in which the data is inputted is selected by the column decoder 3.
The word line control circuit 6 is connected to the memory cell array 1. The word line control circuit 6 selects any of the word lines of the memory cell array 1, and supplies a voltage necessary for reading, writing or erasing the data to the selected word line.
The memory cell array 1, bit line control circuit 2, column decoder 3, data input/output circuit 4 and word line control circuit 6 are connected to a control signal generating circuit 7a and a control voltage generating circuit 7b, and controlled by the control signal generating circuit 7a and the control voltage generating circuit 7b. The control signal generating circuit 7a and the control voltage generating circuit 7b are connected to a control signal input terminal 8. The respective components 1-4 and 6 of the memory cell array 1 are controlled by a control signal inputted to the control signal input terminal 8 from outside. The control voltage generating circuit 7b generates voltages respectively required for programming, verifying, reading, and erasing the data to supply the generated voltages to the components 1-4 and 6 of the memory cell array 1.
There is a problem that the data writing operation must is executed according to a “forward direction” as first page→second page in the conventional multiple-value memory cells described above. The problem is described in detail as follows.
When the data in the first page is written in the conventional multiple-value memory cell in the erased state, that is, the state “0” (data “11), the write data “1” and the write state “0” respectively shift to “0” (data “11) or “1” (data “10) in the memory cell. When the data in the second page is subsequently written in the current state, the write data “1” and the write data “0” respectively shift to any of “0” (data “11”), “1” (data “10”), “2” (data “00”) and “3” (data “01”) in the memory cell (processing according to the forward order, first page→second page).
However, when the data is written in a “reverse direction” in which the data in the second page is written in the erased state before the data in the first page is written, the write data of the second page “1” and “0” respectively shift to “0” (data “11”) and “3” (data “01”).
In the case of memory cells of floating gate type such as the NAND flash memory or the like, the threshold value of the memory cells is made higher by the data write operation, while lower by the data erasing. Therefore, it is not possible to change “3”, which is the highest threshold voltage in the four states in the writing operation, back to “1” or “2”. Then, the data in the first page cannot be written in the writing operation in the “reverse direction” because there trouble is generated in a sequential shift of the memory cell (threshold voltage). As a result, the data cannot be recorded as the multiple-value memory. Due to the disadvantage, the conventional writing operation could be limitedly executed only in the “forward direction”, first page→second page, there has been a problem that it is not possible to write the data in the multiple-value flash memory at random addresses.